Recently, there is strong demand for low power consumption because of rapid distribution of portable devices such as notebook computers and handheld computers. Therefore, a double data rate (DDR) DRAM has been widely used because of its high speed and low power consumption.
The DDR DRAM mostly uses 2.5 volts (V) or 3.3 volts (V) as a power voltage. Thus, a number of devices which can selectively use either 2.5 V or 3.3 V in one DRAM have been designed for different options.
In addition to the DDR DRAM, a number of combination devices, which can selectively use an external power voltage, have been designed in a field of a single data rate (SDR) DRAM. To select good products among the combination devices, an operation life test for testing an operation life of the devices under poor conditions and a burn-in test are performed.
FIG. 1 is a schematic diagram of a conventional semiconductor memory test device. The conventional semiconductor memory test device includes a reference voltage generating unit 1, a core voltage amplifying unit 2, a peri voltage amplifying unit 3, a core voltage comparing unit 4, a peri voltage comparing unit 5, a core voltage driving unit 6, a peri voltage driving unit 7, a VPP generating unit 8, a VBB generating unit 9, a VCP/VBLP generating unit 10, a core stress voltage generating unit 12 and a peri stress voltage generating unit 13.
Here, an amplifier A1 of the core voltage amplifying unit 2 receives a reference voltage from the reference voltage generating unit 1 through its positive (+) terminal. The negative (−) terminal of the amplifier A1 is connected to a common node of resistors R1 and R2. The amplifier A1 outputs a core reference voltage VREFC through its output terminal, which is coupled to the resistor R1.
An amplifier A2 of the peri voltage amplifying unit 3 receives the reference voltage from the reference voltage generating unit 1 through its positive (+) terminal. The negative (−) terminal of the amplifier A2 is connected to a common node of resistors R3 and R4. The amplifier A2 outputs a peri reference voltage VREFP through its output terminal, which is coupled to the resistor R3.
The core stress voltage generating unit 12 generates a core stress voltage VSTRESSC when a test signal TEST is enabled. An inverter IV1 inverts the test signal TEST to produce an inverted test signal/TEST. A PMOS transistor P1 has its source terminal configured to receive an external power voltage VDD and its gate terminal configured to receive the inverted test signal/TEST. An NMOS transistor N1 has its gate terminal and drain terminal commonly connected to a drain terminal of the PMOS transistor P1 in a diode type. An NMOS transistor N2 has its gate terminal and drain terminal commonly connected to a source terminal of the NMOS transistor N1 in a diode type.
The peri stress voltage generating unit 13 outputs a peri stress voltage VSTRESSP when the test signal TEST is enabled. An inverter IV2 inverts the test signal TEST to produce the inverted test signal/TEST. A PMOS transistor P2 has its source terminal to receive the external power voltage VDD and its gate terminal to receive the inverted test signal/TEST. An NMOS transistor N3 has its gate terminal and drain terminal commonly connected to a drain terminal of the PMOS transistor P2 in a diode type. An NMOS transistor N4 has its gate terminal and drain terminal commonly connected to a source terminal of the NMOS transistor N3 in a diode type.
A basic flow of the conventional semiconductor memory test device is described below. When the test signal TEST inputted to the core stress voltage generating unit 12 is a high level, the inverted test signal/TEST inverted by the inverter IV1 is inputted into the PMOS transistor P1 to turn on the PMOS transistor P1. When the PMOS transistor P1 is turned on, the external power voltage VDD is applied to the core stress voltage generating unit 12. Accordingly, the NMOS transistors N1 and N2 composing the diode drop the external voltage VCC by 2Vt (Vt is a threshold voltage) and output the dropped voltage. Therefore, the core stress voltage generating unit 12 outputs VDD-2Vt as the core stress voltage VSTRESSC.
The core voltage comparing unit 4 compares the core reference voltage VREFC from the core voltage amplifying unit 2 with the core stress voltage VSTRESSC from the core stress voltage generating unit 12, and outputs a voltage having a higher potential level of the two voltages (i.e., VREFC or VSTRESSC). The core voltage driving unit 6 receives the voltage from the core voltage comparing unit 4, and outputs a core voltage VCORE.
Accordingly, when the external power voltage VDD is VDD1+2Vt (hereinafter, VDD1 is a predetermined voltage value of the external power voltage VDD), a level gradient of the core voltage VCORE is varied. In addition, the VPP generating unit 8 outputs a pumping voltage VPP by using the core voltage CORE from the core voltage driving unit 6 as a reference voltage in response to the test signal TEST.
On the other hand, when the test signal TEST inputted to the peri stress voltage generating unit 13 is a high level, the inverted test signal/TEST inverted by the inverter IV2 is inputted into the PMOS transistor P2 to turn on the PMOS transistor P2. When the PMOS transistor P2 is turned on, the external power voltage VDD is applied to the peri stress voltage generating unit 13. Accordingly, the NMOS transistors N3 and N4 composing the diode drop the external power voltage VCC by 1Vt+α and output the dropped voltage. Therefore, the peri stress voltage generating unit 13 outputs VDD−1Vt−α as the peri stress voltage VSTRESSP.
The peri voltage comparing unit 5 compares the peri reference voltage VREFP from the peri voltage amplifying unit 3 with the peri stress voltage VSTRESSP from the peri stress voltage generating unit 13, and outputs a voltage having a higher potential level of the two voltages (i.e., VREFP or VSTRESSP). The peri voltage driving unit 7 receives the voltage from the peri voltage comparing unit 5, and outputs a peri voltage VPERI. Accordingly, when the external power voltage VDD is VDD1+1Vt+α, a level gradient of the peri voltage VPERI is varied. In response to the test signal TEST, the VPP generating unit 8 and the VBB generating unit 9 output the pumping voltage VPP and back bias voltage VBB of wanted level, respectively, which are used in the operation life test or the burn-in test.
FIG. 2a is a voltage graph in a state where the normal operation, operation life test operation and burn-in test operation are mixed in the conventional semiconductor memory test device for 3.3 V. As shown in FIG. 2a, when the external power voltage VDD is 3.3 V, it can be varied into 3.8 V during the normal operation. When the external power voltage VDD is 4.0 V, the level gradient of the core voltage VCORE is varied during the test operation.
The time point when the level gradient of the core voltage VCORE is varied must be determined with a margin considering the varing PVT (parameter, voltage and temperature). That is, when the level of the core voltage VCORE is 2.3 V under conditions of the high temperature and low speed test, the level gradient of the core voltage VCORE is varied if the external power voltage VDD is 4.0 V. Therefore, when the external power voltage VDD is at least 4.3 V, the level gradients of the peri voltage VPERI and the core voltage VCORE must be varied during the normal operation.
FIG. 2b is a voltage graph in a state where the normal operation, operation life test operation and burn-in test operation are mixed in the conventional semiconductor memory test device for 2.5 V. As depicted in FIG. 2b, if the external power voltage VDD is 2.5 V, the external power voltage VDD may vary up to 3.0 V during the normal operation. In addition, when the external power voltage VDD is 3.0 V, the level gradient of the core voltage VCORE is varied during the test.
The conventional semiconductor memory test device generates the pumping voltage VPP, bit line precharge voltage VBLP, cell plate voltage VCP and back bias voltage VBB by using the core voltage VCORE as the reference voltage in an OP region for performing the operation life test or a BI region for performing the burn-in test. Therefore, when the level of the core voltage VCORE is varied during the operation life test or the burn-in test, the level of the pumping voltage VPP is also varied. That is, region (B) of FIG. 2a shows a region where the level of the pumping voltage VPP is lower than that of the external power voltage VDD because of level variations of the core voltage VCORE. In this case, forward bias is generated between the external power voltage VDD and the pumping voltage VPP in the VPP generating unit 8 for generating the pumping voltage VPP. As a result, there is a problem in that a direct path is formed between the external power voltage VDD and the pumping voltage VPP. Thus, the level of the pumping voltage VPP is increased according to the level of the external power voltage VDD.